It has long been desirable to be able to pack as many chips into as small a space as possible. More recently, this has led to the development of various integration techniques.
One such integration method, shown in FIG. 1, involves directly attaching one die 102 onto a second die 104. This allows the top die 102 and bottom die 104 to communicate directly with each other. In addition, the two chips 102, 104 are externally connected using wirebonds 106 connected to the chip(s) via a routing trace 108. While this approach results in a smaller package, it also results in a problem if the two chips are the same size or of nearly the same size, because, in some cases, there might not be enough room for wirebond pads 110 to exist on one of the dies. Moreover, using this approach with multiple chips (e.g. by stacking several of these two chip units on top of one another in a multi-chip on multi-chip arrangement is both difficult and expensive if wirebonds 106 must be used.
Another integration option, shown in FIG. 2, is to use solder ball 202, flip-chip attachment methods to allow the two die stack to be externally connected. This approach is cheaper than the wirebond approach and, thus, can allow some of the multi-chip on multi-chip arrangements (FIG. 3) to be more easily or cheaply achieved. However, this integration option suffers from the same problem as noted above if the two chips are the same or nearly the same size, because there might not be enough room for solder ball pads to exist on one of the dies.
Still further, the process of stacking the multi-chips (FIG. 3) would require each of the dies to be very, very thin so that the height of the chip 102 that would attach to the chip 104 containing the solder bump pads will be less than the height of a solder ball bump 202 itself Compounding the problem is the fact that the multi-chip on multi-chip stack's overall height will likely also have to be small so that it can fit within standard packages. This requires handling many wafers or dies that are very thin and then performing dual side processing on these thin wafers. As a result, there is a significant risk of yield loss and damage to dies, especially if solder balls 202 must be mounted on those very thin pieces.
Yet another integration option, shown in FIG. 4, is to use a passive device known as an “interposer” 402 that can act as a routing element to connect the two dies together and externally. This approach has the advantage that it eliminates the issue of whether the two dies 404, 406 are identical or close in size because it can always be made big enough to accommodate a wirebond or solder bump connection. However, interposers typically also have has significant drawbacks. For example, they usually require fabrication of an entirely new part (the interposer with its attendant routing 408) which could be complicated and expensive. Moreover, the typical interposer option does not eliminate the issue of handling very thin wafers or doing dual-side processing of those very thin wafers, so the above-mentioned decreased yield and increased damage risks remain. Still further, interposers are typically very thick, so, even if the interposer has through-connections 408, the length of the connections between the two dies are now larger, so the electrical performance of the chip to chip connection can be degraded.
The interposer option also does not dispense with the problems noted above with creating a multi-chip to multi-chip stack (FIG. 5).
In addition, with such an approach it may be necessary to use vias in chips containing active devices which, in some applications, might not be desirable because they take up potential circuit area, increase the risk of yield loss, or both.
Yet further, to add a third ‘chip’ to the stack, each of the individual chips must be even thinner than the option that only had two chips, thereby further adding to the risks of decreased yield and damage.
Thus, there is a need for a packaging option that does not suffer from the problems and/or risks presented by the foregoing options presently available.